The present disclosure relates to a method for driving flash memory devices, and more particularly to a method for programming NAND flash memory devices.
Generally, a semiconductor device used for storing data can be classified into a volatile memory device and a non-volatile memory device. The volatile memory device loses the stored data as the power supply is interrupted, whereas the non-volatile memory device maintains the stored data even though the power supply is interrupted. Therefore, the non-volatile memory device is widely used under a circumstance that the power source can not be always used and is often interrupted, such as a mobile phone system, a memory card used for storing music and/or video data or other application devices, or when a low power is required to be used. A representative example of such non-volatile memory device can be exemplified by a flash memory device.
The flash memory device is classified into a floating gate-type and a charge trap-type in accordance with a kind of a storage layer. The floating gate-type flash memory accumulates charges into a floating gate and the charge trap-type flash memory accumulates charges in a trap site which exists in a charge trap layer such as Silicone Nitride (SiN).
The charge trap-type flash memory device has a SONOS-type structure in which a tunneling layer of oxide film, a charge trap layer of Nitride film, a blocking layer of oxide film and a control gate electrode of poly-silicon film are laminated on a semiconductor substrate in order; or a MANOS-type structure in which a tunneling layer of oxide film, a charge trap layer of nitride film, a blocking layer of aluminum oxide film and a control gate electrode of metal are laminated on the semiconductor substrate in order.
The charge trap-type flash memory device which has been widely used is programmed on a page-unit basis sequentially from a first word line WL0 to a last word line WL31 if it has, for example, 32 cell strings. However, since the first word line WL0 programmed initially is operated in a program inhibit mode while other word lines are programmed, a change in a threshold voltage is caused due to a pass disturbance.
FIG. 1 is a circuit diagram showing a NAND flash memory device illustrating a prior program method, and FIG. 2 is a graph illustrating the change in the threshold voltage of the programmed memory cell as caused by the pass disturbance.
Referring to FIG. 1, the memory cell array is configured with a plurality of cell strings connected to a bit line BL. The cell string is consisted of a source select transistor 110, a plurality of memory cell transistors 131˜136, and a drain select transistor 120. The source select transistors 110 have gates connected to a source select line SSL in common and the drain select transistors 120 have gates connected to a drain select line DSL in common. The memory cell transistors 131˜136 have control gates connected to the word lines WL0˜WL31. The memory cell transistors 131˜136 are connected in series between the source select transistor 110 and the drain select transistor 120. The number of the memory cells included within a single cell string is 32 as shown or the number can be changed depending on a storage capacity of the memory device. The source select transistor 110 and the drain select transistor 120 are a typical MOS transistor and the memory cell transistors 131˜136 are charge trap-type transistors.
The program of the memory cells is proceeded on a page-unit basis sequentially from the memory cell 131 connected to the first word line WL0 to the memory cell 136 connected to the last word line WL31. For example, when programming the memory cell 132 connected to the second word line WL1 after programming the memory cell connected to the first word line WL0, a program voltage Vpgm is applied to the word line of the memory cell 132 to be programmed and a pass voltage Vpass is applied to remaining word lines. At this time, the memory cell 131 connected to the first word line which is already programmed is operated in the program inhibit mode so that the threshold voltage distribution 210 is gradually moved rightward, as shown in FIG. 2. To the memory cell 131 which is initially programmed, the pass voltage is applied 31 times so that the memory cell 131 is substantially subject to the pass disturbance, which results that the threshold voltage distribution is largely moved. Because a correct verification is not performed in a program verification step if the threshold voltage distribution of the memory cell moves, the program fail can be encountered which is not capable of being programmed in a desirable level and the data can not be correctly read out in a read operation.